/*
 * @Author: Laputa
 * @Version: V0.0
 * @Date: 2023-09-15 16:44:57
 * @LastEditors: Laputa
 * @LastEditTime: 2023-09-23 16:59:45
 * @Description: This file contains the functions prototypes for the CLOCK firmware library.
 * 
 * Copyright (c) 2023 by Levetop, All Rights Reserved. 
 */

#ifndef _LT168_CLOCK_H
#define _LT168_CLOCK_H

#include "lt168.h"


extern uint32_t SYS_CLOCK;
extern uint32_t OSC;//澶栭儴鏃堕挓

/*
1. 1MHz <= XIN/N <= 50MHZ
2. 200MHz <= XIN*M/N <= 400MHz
3. M
4. N
*/
typedef struct
{
	unsigned short M;	//4<=M , 4-16383
	unsigned char  N;	//1<=N , 1-15
	unsigned char OD;	//0-3, 2^OD (1,2,4,8)
	unsigned char DIV;	//0-63, 0: by 2,DRV = value*2;
	unsigned long OSC;	//澶栭儴鏅舵尟鍥哄畾涓�12MHz
}PLL_Set_parameter;

uint32_t Get_SysClock(void);
void Clock_Init(UINT32 sys_clk_mhz);

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define PLL_M     (400)
#define PLL_N     (12)
#define PLL_OD    (0)
#define PLL_DIV   (0)
#define LT168_OSC (12000000U)

/* SYNCR */
#define CLOCK_SYNCR_LOSCLPEN_MASK        (0x1U)
#define CLOCK_SYNCR_LOSCLPEN_SHIFT       (0U)
#define CLOCK_SYNCR_LOSCLPEN(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_LOSCLPEN_SHIFT)) & CLOCK_SYNCR_LOSCLPEN_MASK)

#define CLOCK_SYNCR_ADCEN_MASK           (0x4U)
#define CLOCK_SYNCR_ADCEN_SHIFT          (2U)
#define CLOCK_SYNCR_ADCEN(x)             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ADCEN_SHIFT)) & CLOCK_SYNCR_ADCEN_MASK)

#define CLOCK_SYNCR_CACHERAMLPEN_MASK    (0x8U)
#define CLOCK_SYNCR_CACHERAMLPEN_SHIFT   (3U)
#define CLOCK_SYNCR_CACHERAMLPEN(x)      (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_CACHERAMLPEN_SHIFT)) & CLOCK_SYNCR_CACHERAMLPEN_MASK)

#define CLOCK_SYNCR_STBYMD_MASK          (0x30U)
#define CLOCK_SYNCR_STBYMD_SHIFT         (4U)
#define CLOCK_SYNCR_STBYMD(x)            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_STBYMD_SHIFT)) & CLOCK_SYNCR_STBYMD_MASK)

#define CLOCK_SYNCR_CLKOUTSEL_MASK       (0x40U)
#define CLOCK_SYNCR_CLKOUTSEL_SHIFT      (6U)
#define CLOCK_SYNCR_CLKOUTSEL(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_CLKOUTSEL_SHIFT)) & CLOCK_SYNCR_CLKOUTSEL_MASK)

#define CLOCK_SYNCR_DISPLAYRAMLPEN_MASK  (0x80U)
#define CLOCK_SYNCR_DISPLAYRAMLPEN_SHIFT (7U)
#define CLOCK_SYNCR_DISPLAYRAMLPEN(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_DISPLAYRAMLPEN_SHIFT)) & CLOCK_SYNCR_DISPLAYRAMLPEN_MASK)

#define CLOCK_SYNCR_SLEEP_MASK           (0x100U)
#define CLOCK_SYNCR_SLEEP_SHIFT          (8U)
#define CLOCK_SYNCR_SLEEP(x)             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SLEEP_SHIFT)) & CLOCK_SYNCR_SLEEP_MASK)

#define CLOCK_SYNCR_PLLEN_MASK           (0x200U)
#define CLOCK_SYNCR_PLLEN_SHIFT          (9U)
#define CLOCK_SYNCR_PLLEN(x)             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLEN_SHIFT)) & CLOCK_SYNCR_PLLEN_MASK)

#define CLOCK_SYNCR_PLLSRCEN_MASK        (0x400U)
#define CLOCK_SYNCR_PLLSRCEN_SHIFT       (10U)
#define CLOCK_SYNCR_PLLSRCEN(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLSRCEN_SHIFT)) & CLOCK_SYNCR_PLLSRCEN_MASK)

#define CLOCK_SYNCR_LOSCEN_MASK          (0x800U)
#define CLOCK_SYNCR_LOSCEN_SHIFT         (11U)
#define CLOCK_SYNCR_LOSCEN(x)            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_LOSCEN_SHIFT)) & CLOCK_SYNCR_LOSCEN_MASK)

#define CLOCK_SYNCR_ADCDIV_MASK          (0xF000U)
#define CLOCK_SYNCR_ADCDIV_SHIFT         (12U)
#define CLOCK_SYNCR_ADCDIV(x)            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ADCDIV_SHIFT)) & CLOCK_SYNCR_ADCDIV_MASK)

#define CLOCK_SYNCR_PLLDIV_MASK          (0xFC0000U)
#define CLOCK_SYNCR_PLLDIV_SHIFT         (18U)
#define CLOCK_SYNCR_PLLDIV(x)            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLDIV_SHIFT)) & CLOCK_SYNCR_PLLDIV_MASK)

#define CLOCK_SYNCR_ENLOWPOWER_MASK      (0x1000000U)
#define CLOCK_SYNCR_ENLOWPOWER_SHIFT     (24U)
#define CLOCK_SYNCR_ENLOWPOWER(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ENLOWPOWER_SHIFT)) & CLOCK_SYNCR_ENLOWPOWER_MASK)

#define CLOCK_SYNCR_PLLOCKM_MASK         (0x2000000U)
#define CLOCK_SYNCR_PLLOCKM_SHIFT        (25U)
#define CLOCK_SYNCR_PLLOCKM(x)           (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLOCKM_SHIFT)) & CLOCK_SYNCR_PLLOCKM_MASK)

#define CLOCK_SYNCR_SYSRAM0LPEN_MASK     (0x4000000U)
#define CLOCK_SYNCR_SYSRAM0LPEN_SHIFT    (26U)
#define CLOCK_SYNCR_SYSRAM0LPEN(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM0LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM0LPEN_MASK)

#define CLOCK_SYNCR_SYSRAM1LPEN_MASK     (0x8000000U)
#define CLOCK_SYNCR_SYSRAM1LPEN_SHIFT    (27U)
#define CLOCK_SYNCR_SYSRAM1LPEN(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM1LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM1LPEN_MASK)

#define CLOCK_SYNCR_SYSRAM2LPEN_MASK     (0x10000000U)
#define CLOCK_SYNCR_SYSRAM2LPEN_SHIFT    (28U)
#define CLOCK_SYNCR_SYSRAM2LPEN(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM2LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM2LPEN_MASK)

#define CLOCK_SYNCR_SYSRAM3LPEN_MASK     (0x20000000U)
#define CLOCK_SYNCR_SYSRAM3LPEN_SHIFT    (29U)
#define CLOCK_SYNCR_SYSRAM3LPEN(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM3LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM3LPEN_MASK)

#define CLOCK_SYNCR_SYNCTEST_MASK        (0xC0000000U)
#define CLOCK_SYNCR_SYNCTEST_SHIFT       (30U)
#define CLOCK_SYNCR_SYNCTEST(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYNCTEST_SHIFT)) & CLOCK_SYNCR_SYNCTEST_MASK)

/* LOSCCSR */
#define CLOCK_LOSCCSR_SXOSCEN_MASK        (0x1U)
#define CLOCK_LOSCCSR_SXOSCEN_SHIFT       (0U)
#define CLOCK_LOSCCSR_SXOSCEN(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SXOSCEN_SHIFT)) & CLOCK_LOSCCSR_SXOSCEN_MASK)

#define CLOCK_LOSCCSR_WDTCLKSEL_MASK      (0x2U)
#define CLOCK_LOSCCSR_WDTCLKSEL_SHIFT     (1U)
#define CLOCK_LOSCCSR_WDTCLKSEL(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_WDTCLKSEL_SHIFT)) & CLOCK_LOSCCSR_WDTCLKSEL_MASK)

#define CLOCK_LOSCCSR_WDTCLKCHGDONE_MASK  (0x20U)
#define CLOCK_LOSCCSR_WDTCLKCHGDONE_SHIFT (5U)

#define CLOCK_LOSCCSR_SXOSCRDY_MASK       (0x40U)
#define CLOCK_LOSCCSR_SXOSCRDY_SHIFT      (6U)

#define CLOCK_LOSCCSR_SIRCRDY_MASK        (0x80U)
#define CLOCK_LOSCCSR_SIRCRDY_SHIFT       (7U)

#define CLOCK_LOSCCSR_SXOSCST_MASK        (0xFFFF00U)
#define CLOCK_LOSCCSR_SXOSCST_SHIFT       (8U)
#define CLOCK_LOSCCSR_SXOSCST(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SXOSCST_SHIFT)) & CLOCK_LOSCCSR_SXOSCST_MASK)

#define CLOCK_LOSCCSR_SIRCST_MASK         (0x1F000000U)
#define CLOCK_LOSCCSR_SIRCST_SHIFT        (24U)
#define CLOCK_LOSCCSR_SIRCST(x)           (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SIRCST_SHIFT)) & CLOCK_LOSCCSR_SIRCST_MASK)

#define CLOCK_LOSCCSR_LOSCCSTEST_MASK     (0xC0000000U)
#define CLOCK_LOSCCSR_LOSCCSTEST_SHIFT    (30U)
#define CLOCK_LOSCCSR_LOSCCSTEST(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_LOSCCSTEST_SHIFT)) & CLOCK_LOSCCSR_LOSCCSTEST_MASK)

/* PLLCSR */
#define CLOCK_PLLCSR_PLLM_MASK        (0x3FFFU)
#define CLOCK_PLLCSR_PLLM_SHIFT       (0U)
#define CLOCK_PLLCSR_PLLM(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLM_SHIFT)) & CLOCK_PLLCSR_PLLM_MASK)

#define CLOCK_PLLCSR_PLLOD_MASK       (0xC000U)
#define CLOCK_PLLCSR_PLLOD_SHIFT      (14U)
#define CLOCK_PLLCSR_PLLOD(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLOD_SHIFT)) & CLOCK_PLLCSR_PLLOD_MASK)

#define CLOCK_PLLCSR_PLLN_MASK        (0xF0000U)
#define CLOCK_PLLCSR_PLLN_SHIFT       (16U)
#define CLOCK_PLLCSR_PLLN(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLN_SHIFT)) & CLOCK_PLLCSR_PLLN_MASK)

#define CLOCK_PLLCSR_PLLOCK_MASK      (0x01000000U)
#define CLOCK_PLLCSR_PLLOCK_SHIFT     (24U)

#define CLOCK_PLLCSR_PLLCSRTEST_MASK  (0xC0000000U)
#define CLOCK_PLLCSR_PLLCSRTEST_SHIFT (30U)
#define CLOCK_PLLCSR_PLLCSRTEST(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLCSRTEST_SHIFT)) & CLOCK_PLLCSR_PLLCSRTEST_MASK)

/* MSCR */

#define CLOCK_MSCR_BLENDER_MASK   (0x1U)
#define CLOCK_MSCR_BLENDER_SHIFT  (0U)
#define CLOCK_MSCR_BLENDER(x)     (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_BLENDER_SHIFT)) & CLOCK_MSCR_BLENDER_MASK)

#define CLOCK_MSCR_COMP0_MASK     (0x2U)
#define CLOCK_MSCR_COMP0_SHIFT    (1U)
#define CLOCK_MSCR_COMP0(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_COMP0_SHIFT)) & CLOCK_MSCR_COMP0_MASK)

#define CLOCK_MSCR_COMP1_MASK     (0x4U)
#define CLOCK_MSCR_COMP1_SHIFT    (2U)
#define CLOCK_MSCR_COMP1(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_COMP1_SHIFT)) & CLOCK_MSCR_COMP1_MASK)

#define CLOCK_MSCR_ADC_MASK       (0x8U)
#define CLOCK_MSCR_ADC_SHIFT      (3U)
#define CLOCK_MSCR_ADC(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_ADC_SHIFT)) & CLOCK_MSCR_ADC_MASK)

#define CLOCK_MSCR_PIT0_MASK      (0x10U)
#define CLOCK_MSCR_PIT0_SHIFT     (4U)
#define CLOCK_MSCR_PIT0(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT0_SHIFT)) & CLOCK_MSCR_PIT0_MASK)

#define CLOCK_MSCR_PIT1_MASK      (0x20U)
#define CLOCK_MSCR_PIT1_SHIFT     (5U)
#define CLOCK_MSCR_PIT1(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT1_SHIFT)) & CLOCK_MSCR_PIT1_MASK)

#define CLOCK_MSCR_PIT2_MASK      (0x40U)
#define CLOCK_MSCR_PIT2_SHIFT     (6U)
#define CLOCK_MSCR_PIT2(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT2_SHIFT)) & CLOCK_MSCR_PIT2_MASK)

#define CLOCK_MSCR_PIT3_MASK      (0x80U)
#define CLOCK_MSCR_PIT3_SHIFT     (7U)
#define CLOCK_MSCR_PIT3(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT3_SHIFT)) & CLOCK_MSCR_PIT3_MASK)

#define CLOCK_MSCR_RTC_MASK       (0x100U)
#define CLOCK_MSCR_RTC_SHIFT      (8U)
#define CLOCK_MSCR_RTC(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RTC_SHIFT)) & CLOCK_MSCR_RTC_MASK)

#define CLOCK_MSCR_DMA_MASK       (0x200U)
#define CLOCK_MSCR_DMA_SHIFT      (9U)
#define CLOCK_MSCR_DMA(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_DMA_SHIFT)) & CLOCK_MSCR_DMA_MASK)

#define CLOCK_MSCR_PWM0_MASK      (0x400U)
#define CLOCK_MSCR_PWM0_SHIFT     (10U)
#define CLOCK_MSCR_PWM0(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PWM0_SHIFT)) & CLOCK_MSCR_PWM0_MASK)

#define CLOCK_MSCR_PWM1_MASK      (0x800U)
#define CLOCK_MSCR_PWM1_SHIFT     (11U)
#define CLOCK_MSCR_PWM1(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PWM1_SHIFT)) & CLOCK_MSCR_PWM1_MASK)

#define CLOCK_MSCR_EPORT0_MASK    (0x1000U)
#define CLOCK_MSCR_EPORT0_SHIFT   (12U)
#define CLOCK_MSCR_EPORT0(x)      (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT0_SHIFT)) & CLOCK_MSCR_EPORT0_MASK)

#define CLOCK_MSCR_EPORT1_MASK    (0x2000U)
#define CLOCK_MSCR_EPORT1_SHIFT   (13U)
#define CLOCK_MSCR_EPORT1(x)      (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT1_SHIFT)) & CLOCK_MSCR_EPORT1_MASK)

#define CLOCK_MSCR_XBAR_MASK      (0x4000U)
#define CLOCK_MSCR_XBAR_SHIFT     (14U)
#define CLOCK_MSCR_XBAR(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_XBAR_SHIFT)) & CLOCK_MSCR_XBAR_MASK)

#define CLOCK_MSCR_OPTION_MASK    (0x8000U)
#define CLOCK_MSCR_OPTION_SHIFT   (15U)
#define CLOCK_MSCR_OPTION(x)      (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_OPTION_SHIFT)) & CLOCK_MSCR_OPTION_MASK)

#define CLOCK_MSCR_RESET_MASK     (0x10000U)
#define CLOCK_MSCR_RESET_SHIFT    (16U)
#define CLOCK_MSCR_RESET(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RESET_SHIFT)) & CLOCK_MSCR_RESET_MASK)

#define CLOCK_MSCR_WDT_MASK       (0x20000U)
#define CLOCK_MSCR_WDT_SHIFT      (17U)
#define CLOCK_MSCR_WDT(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_WDT_SHIFT)) & CLOCK_MSCR_WDT_MASK)

#define CLOCK_MSCR_SCI0_MASK      (0x40000U)
#define CLOCK_MSCR_SCI0_SHIFT     (18U)
#define CLOCK_MSCR_SCI0(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI0_SHIFT)) & CLOCK_MSCR_SCI0_MASK)

#define CLOCK_MSCR_CCM_MASK       (0x80000U)
#define CLOCK_MSCR_CCM_SHIFT      (19U)
#define CLOCK_MSCR_CCM(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_CCM_SHIFT)) & CLOCK_MSCR_CCM_MASK)

#define CLOCK_MSCR_I2C_MASK       (0x100000U)
#define CLOCK_MSCR_I2C_SHIFT      (20U)
#define CLOCK_MSCR_I2C(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_I2C_SHIFT)) & CLOCK_MSCR_I2C_MASK)

#define CLOCK_MSCR_SCI1_MASK      (0x200000U)
#define CLOCK_MSCR_SCI1_SHIFT     (21U)
#define CLOCK_MSCR_SCI1(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI1_SHIFT)) & CLOCK_MSCR_SCI1_MASK)

#define CLOCK_MSCR_SCI2_MASK      (0x400000U)
#define CLOCK_MSCR_SCI2_SHIFT     (22U)
#define CLOCK_MSCR_SCI2(x)        (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI2_SHIFT)) & CLOCK_MSCR_SCI2_MASK)

#define CLOCK_MSCR_CAN_MASK       (0x800000U)
#define CLOCK_MSCR_CAN_SHIFT      (23U)
#define CLOCK_MSCR_CAN(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_CAN_SHIFT)) & CLOCK_MSCR_CAN_MASK)

#define CLOCK_MSCR_EPORT2_MASK    (0x1000000U)
#define CLOCK_MSCR_EPORT2_SHIFT   (24U)
#define CLOCK_MSCR_EPORT2(x)      (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT2_SHIFT)) & CLOCK_MSCR_EPORT2_MASK)

#define CLOCK_MSCR_QSPI0_MASK     (0x2000000U)
#define CLOCK_MSCR_QSPI0_SHIFT    (25U)
#define CLOCK_MSCR_QSPI0(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI0_SHIFT)) & CLOCK_MSCR_QSPI0_MASK)

#define CLOCK_MSCR_QSPI1_MASK     (0x4000000U)
#define CLOCK_MSCR_QSPI1_SHIFT    (26U)
#define CLOCK_MSCR_QSPI1(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI1_SHIFT)) & CLOCK_MSCR_QSPI1_MASK)

#define CLOCK_MSCR_QSPI2_MASK     (0x8000000U)
#define CLOCK_MSCR_QSPI2_SHIFT    (27U)
#define CLOCK_MSCR_QSPI2(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI2_SHIFT)) & CLOCK_MSCR_QSPI2_MASK)

#define CLOCK_MSCR_RGB_MASK       (0x10000000U)
#define CLOCK_MSCR_RGB_SHIFT      (28U)
#define CLOCK_MSCR_RGB(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RGB_SHIFT)) & CLOCK_MSCR_RGB_MASK)

#define CLOCK_MSCR_USB_MASK       (0x20000000U)
#define CLOCK_MSCR_USB_SHIFT      (29U)
#define CLOCK_MSCR_USB(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_USB_SHIFT)) & CLOCK_MSCR_USB_MASK)

#define CLOCK_MSCR_MSCRTEST_MASK  (0xC0000000U)
#define CLOCK_MSCR_MSCRTEST_SHIFT (30U)
#define CLOCK_MSCR_MSCRTEST(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_MSCRTEST_SHIFT)) & CLOCK_MSCR_MSCRTEST_MASK)

/* ECSECR */

#define CLOCK_ECSECR_EPTEN_MASK   (0x800000U)
#define CLOCK_ECSECR_EPTEN_SHIFT  (23U)
#define CLOCK_ECSECR_EPTEN(x)     (((uint32_t)(((uint32_t)(x)) << CLOCK_ECSECR_EPTEN_SHIFT)) & CLOCK_ECSECR_EPTEN_MASK)

#define CLOCK_ECSECR_EPTDIV_MASK  (0xFF000000U)
#define CLOCK_ECSECR_EPTDIV_SHIFT (24U)
#define CLOCK_ECSECR_EPTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_ECSECR_EPTDIV_SHIFT)) & CLOCK_ECSECR_EPTDIV_MASK)

/* OBTCR1 */
#define CLOCK_OBTCR1_BIST_TARGET_MASK       (0xFFFFU)
#define CLOCK_OBTCR1_BIST_TARGET_SHIFT      (0U)
#define CLOCK_OBTCR1_BIST_TARGET(x)         (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR1_BIST_TARGET_SHIFT)) & CLOCK_OBTCR1_BIST_TARGET_MASK)

#define CLOCK_OBTCR1_BIST_HOLD_TARGET_MASK  (0xFFFF0000U)
#define CLOCK_OBTCR1_BIST_HOLD_TARGET_SHIFT (16U)
#define CLOCK_OBTCR1_BIST_HOLD_TARGET(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR1_BIST_HOLD_TARGET_SHIFT)) & CLOCK_OBTCR1_BIST_HOLD_TARGET_MASK)

/* OBTCR2 */
#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_MASK  (0xFFFFU)
#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_SHIFT (0U)
#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_SHIFT)) & CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_MASK)

#define CLOCK_OBTCR2_BIST_TEST_TARGET_MASK        (0xFFFF0000U)
#define CLOCK_OBTCR2_BIST_TEST_TARGET_SHIFT       (16U)
#define CLOCK_OBTCR2_BIST_TEST_TARGET(x)          (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR2_BIST_TEST_TARGET_SHIFT)) & CLOCK_OBTCR2_BIST_TEST_TARGET_MASK)

/* OBTCR */
#define CLOCK_OBTCR_BIST_EN_MASK                 (0x100U)
#define CLOCK_OBTCR_BIST_EN_SHIFT                (8U)
#define CLOCK_OBTCR_BIST_EN(x)                   (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_EN_SHIFT)) & CLOCK_OBTCR_BIST_EN_MASK)

#define CLOCK_OBTCR_BIST_IRC_SEL_MASK            (0x200U)
#define CLOCK_OBTCR_BIST_IRC_SEL_SHIFT           (9U)
#define CLOCK_OBTCR_BIST_IRC_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_IRC_SEL_SHIFT)) & CLOCK_OBTCR_BIST_IRC_SEL_MASK)

#define CLOCK_OBTCR_BIST_IRC_EN_MASK             (0x400U)
#define CLOCK_OBTCR_BIST_IRC_EN_SHIFT            (10U)
#define CLOCK_OBTCR_BIST_IRC_EN(x)               (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_IRC_EN_SHIFT)) & CLOCK_OBTCR_BIST_IRC_EN_MASK)

#define CLOCK_OBTCR_BIST_VAL_INV_MASK            (0x800U)
#define CLOCK_OBTCR_BIST_VAL_INV_SHIFT           (11U)
#define CLOCK_OBTCR_BIST_VAL_INV(x)              (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_VAL_INV_SHIFT)) & CLOCK_OBTCR_BIST_VAL_INV_MASK)

#define CLOCK_OBTCR_BIST_MODE_MASK               (0x1000U)
#define CLOCK_OBTCR_BIST_MODE_SHIFT              (12U)
#define CLOCK_OBTCR_BIST_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_MODE_SHIFT)) & CLOCK_OBTCR_BIST_MODE_MASK)

#define CLOCK_OBTCR_BIST_RESETN_MASK             (0x2000U)
#define CLOCK_OBTCR_BIST_RESETN_SHIFT            (13U)
#define CLOCK_OBTCR_BIST_RESETN(x)               (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_RESETN_SHIFT)) & CLOCK_OBTCR_BIST_RESETN_MASK)

#define CLOCK_OBTCR_BIST_START_MASK              (0x8000U)
#define CLOCK_OBTCR_BIST_START_SHIFT             (15U)
#define CLOCK_OBTCR_BIST_START(x)                (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_START_SHIFT)) & CLOCK_OBTCR_BIST_START_MASK)

#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_MASK  (0xFFFF0000U)
#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_SHIFT (16U)
#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_SHIFT)) & CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_MASK)

/* OBTCNTR */
#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE_MASK  (0x1FU)
#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE_SHIFT (0U)
#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_FTRIM_TRACE_SHIFT)) & CLOCK_OBTCNTR_BIST_FTRIM_TRACE_MASK)

#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE_MASK  (0x1F00U)
#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE_SHIFT (8U)
#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE(x)    (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_CTRIM_TRACE_SHIFT)) & CLOCK_OBTCNTR_BIST_CTRIM_TRACE_MASK)

#define CLOCK_OBTCNTR_BIST_TEST_CNT_MASK     (0xFFFF0000U)
#define CLOCK_OBTCNTR_BIST_TEST_CNT_SHIFT    (16U)
#define CLOCK_OBTCNTR_BIST_TEST_CNT(x)       (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_TEST_CNT_SHIFT)) & CLOCK_OBTCNTR_BIST_TEST_CNT_MASK)

/* OBTRR */
#define CLOCK_OBTRR_BISTRESULT_MASK  (0x1FFFFU)
#define CLOCK_OBTRR_BISTRESULT_SHIFT (0U)

#define CLOCK_OBTRR_BIST_PASS_MASK   (0x1000000U)
#define CLOCK_OBTRR_BIST_PASS_SHIFT  (24U)

#define CLOCK_OBTRR_BIST_DONE_MASK   (0x2000000U)
#define CLOCK_OBTRR_BIST_DONE_SHIFT  (25U)

/**
 * @brief: CLOCK PLL Input Divider Enumeration
 */
typedef enum {
    CLOCK_PLL_N_0  = 0U,  /*!< PLL Input Divider 0 */
    CLOCK_PLL_N_1  = 1U,  /*!< PLL Input Divider 1 */
    CLOCK_PLL_N_2  = 2U,  /*!< PLL Input Divider 2 */
    CLOCK_PLL_N_3  = 3U,  /*!< PLL Input Divider 3 */
    CLOCK_PLL_N_4  = 4U,  /*!< PLL Input Divider 4 */
    CLOCK_PLL_N_5  = 5U,  /*!< PLL Input Divider 5 */
    CLOCK_PLL_N_6  = 6U,  /*!< PLL Input Divider 6 */
    CLOCK_PLL_N_7  = 7U,  /*!< PLL Input Divider 7 */
    CLOCK_PLL_N_8  = 8U,  /*!< PLL Input Divider 8 */
    CLOCK_PLL_N_9  = 9U,  /*!< PLL Input Divider 9 */
    CLOCK_PLL_N_10 = 10U, /*!< PLL Input Divider 10 */
    CLOCK_PLL_N_11 = 11U, /*!< PLL Input Divider 11 */
    CLOCK_PLL_N_12 = 12U, /*!< PLL Input Divider 12 */
    CLOCK_PLL_N_13 = 13U, /*!< PLL Input Divider 13 */
    CLOCK_PLL_N_14 = 14U, /*!< PLL Input Divider 14 */
    CLOCK_PLL_N_15 = 15U  /*!< PLL Input Divider 15 */

} clock_pll_n_te;

/**
 * @brief: CLOCK PLL VCO Output Clock Divider Enumeration
 */
typedef enum {
    CLOCK_PLL_OD_1 = 0U, /*!< PLL VCO Output Clock Divider 1 */
    CLOCK_PLL_OD_2 = 1U, /*!< PLL VCO Output Clock Divider 2 */
    CLOCK_PLL_OD_4 = 2U, /*!< PLL VCO Output Clock Divider 4 */
    CLOCK_PLL_OD_8 = 3U, /*!< PLL VCO Output Clock Divider 8 */

} clock_pll_od_te;

/**
 * @brief: CLOCK ADC Clock Divider Enumeration
 */
typedef enum {
    CLOCK_ADC_DIV_0  = 0U,  /*!< ADC Clock Divider 0 */
    CLOCK_ADC_DIV_1  = 1U,  /*!< ADC Clock Divider 1 */
    CLOCK_ADC_DIV_2  = 2U,  /*!< ADC Clock Divider 2 */
    CLOCK_ADC_DIV_3  = 3U,  /*!< ADC Clock Divider 3 */
    CLOCK_ADC_DIV_4  = 4U,  /*!< ADC Clock Divider 4 */
    CLOCK_ADC_DIV_5  = 5U,  /*!< ADC Clock Divider 5 */
    CLOCK_ADC_DIV_6  = 6U,  /*!< ADC Clock Divider 6 */
    CLOCK_ADC_DIV_7  = 7U,  /*!< ADC Clock Divider 7 */
    CLOCK_ADC_DIV_8  = 8U,  /*!< ADC Clock Divider 8 */
    CLOCK_ADC_DIV_9  = 9U,  /*!< ADC Clock Divider 9 */
    CLOCK_ADC_DIV_10 = 10U, /*!< ADC Clock Divider 10 */
    CLOCK_ADC_DIV_11 = 11U, /*!< ADC Clock Divider 11 */
    CLOCK_ADC_DIV_12 = 12U, /*!< ADC Clock Divider 12 */
    CLOCK_ADC_DIV_13 = 13U, /*!< ADC Clock Divider 13 */
    CLOCK_ADC_DIV_14 = 14U, /*!< ADC Clock Divider 14 */
    CLOCK_ADC_DIV_15 = 15U  /*!< ADC Clock Divider 15 */

} clock_adc_clock_divider_te;

/**
 * @brief CLOCK Clock Output Select Mode Enumeration
 */
typedef enum {
    CLOCK_Out_System_Clock = 0U, /*!< Chip Clock Output Pin Output System Clock */
    CLOCK_Out_128KHz_Clock = 1U  /*!< Chip Clock Output Pin Output 128KHz */
} clock_out_select_te;

/**
 * @brief CLOCK Sleep Operation Control Mode Enumeration
 */
typedef enum {
    CLOCK_Sleep_Mode_0 = 0U, /*!< CLOCK_Sleep_Mode_0 */
    CLOCK_Sleep_Mode_1 = 1U, /*!< CLOCK_Sleep_Mode_1 */
    CLOCK_Sleep_Mode_2 = 2U, /*!< CLOCK_Sleep_Mode_2 */
    CLOCK_Sleep_Mode_3 = 3U  /*!< CLOCK_Sleep_Mode_3 */
} clock_sleep_mode_te;

/**
 * @brief CLOCK WatchDog Clock Source Enumeration
 */
typedef enum {
    CLOCK_WatchDog_Source_128K  = 0U, /*!< 128KHz as WatchDog Clock Source */
    CLOCK_WatchDog_Source_32768 = 1U  /*!< 32768 as WatchDog Clock Source */
} clock_watchdog_clock_source_te;

/**
 * @brief CLOCK Module Stop Control Enumeration
 */
typedef enum {
    CLOCK_Module_Stop_BLENDER = 0U,  /*!< Module BLENDER */
    CLOCK_Module_Stop_COMP0   = 1U,  /*!< Module COMP0 */
    CLOCK_Module_Stop_COMP1   = 2U,  /*!< Module COMP1 */
    CLOCK_Module_Stop_ADC     = 3U,  /*!< Module ADC */
    CLOCK_Module_Stop_PIT0    = 4U,  /*!< Module PIT0 */
    CLOCK_Module_Stop_PIT1    = 5U,  /*!< Module PIT1 */
    CLOCK_Module_Stop_PIT2    = 6U,  /*!< Module PIT2 */
    CLOCK_Module_Stop_PIT3    = 7U,  /*!< Module PIT3 */
    CLOCK_Module_Stop_RTC     = 8U,  /*!< Module RTC */
    CLOCK_Module_Stop_DMA     = 9U,  /*!< Module DMA */
    CLOCK_Module_Stop_PWM0    = 10U, /*!< Module PWM0 */
    CLOCK_Module_Stop_PWM1    = 11U, /*!< Module PWM1 */
    CLOCK_Module_Stop_EPORT0  = 12U, /*!< Module EPORT0 */
    CLOCK_Module_Stop_EPORT1  = 13U, /*!< Module EPORT1 */
    CLOCK_Module_Stop_XBAR    = 14U, /*!< Module XBAR */
    CLOCK_Module_Stop_OPTION  = 15U, /*!< Module OPTION */
    CLOCK_Module_Stop_RESET   = 16U, /*!< Module RESET */
    CLOCK_Module_Stop_WDT     = 17U, /*!< Module WDT */
    CLOCK_Module_Stop_SCI0    = 18U, /*!< Module SCI0 */
    CLOCK_Module_Stop_CCM     = 19U, /*!< Module CCM */
    CLOCK_Module_Stop_I2C     = 20U, /*!< Module I2C */
    CLOCK_Module_Stop_SCI1    = 21U, /*!< Module SCI1 */
    CLOCK_Module_Stop_SCI2    = 22U, /*!< Module SCI2 */
    CLOCK_Module_Stop_CAN     = 23U, /*!< Module CAN */
    CLOCK_Module_Stop_EPORT2  = 24U, /*!< Module EPORT2 */
    CLOCK_Module_Stop_QSPI0   = 25U, /*!< Module QSPI0 */
    CLOCK_Module_Stop_QSPI1   = 26U, /*!< Module QSPI1 */
    CLOCK_Module_Stop_QSPI2   = 27U, /*!< Module QSPI2 */
    CLOCK_Module_Stop_RGB     = 28U, /*!< Module RGB */
    CLOCK_Module_Stop_USBC    = 29U  /*!< Module USBC */
} clock_module_stop_te;

/**
 * @brief CLOCK Measurement Source Enumeration
 */
typedef enum {
    CLOCK_Measurement_128K = 0U, /*!< Measuring 128KHz frequency */
    CLOCK_Measurement_PLL  = 1U, /*!< Measuring PLL Output frequency */
} clock_measurement_source_te;

/**
 * @brief CLOCK PLL Configuration Structure Definition
 */
typedef struct
{
    uint16_t m;  /*!< 4<=M , 4-16383 */
    uint8_t n;   /*!< 1<=N ,  1-15 */
    uint8_t od;  /*!< 0-3,   2^OD (1,2,4,8) */
    uint8_t div; /*!< 0-63, 0,1: by 2,DRV = value*2 */
} clock_pll_config_ts;

/*!<---------------End of Definitions--------------->!*/

/*******************************************************************************
 * APIs
 ******************************************************************************/
/* Get System Clock Function */
uint32_t Get_SysClock(void);

/* PLL Initialization Function */
ResultStatus CLOCK_PLL_Init(void);
ResultStatus CLOCK_PLL_Init_flexible(clock_pll_config_ts *pll);

/* Clock Output Setting Function */
void CLOCK_Output_Select(clock_out_select_te select);

/* Sleep Initialization Function */
ResultStatus CLOCK_Sleep_Init(clock_sleep_mode_te mode);

/* ADC Clock Control Function */
void CLOCK_ADC_CLOCK_Init(clock_adc_clock_divider_te div, FunctionState state);

/* WatchDog Clock Source Select Function */
ResultStatus CLOCK_WatchDog_Source_Select(clock_watchdog_clock_source_te source);

/* Module Clock Stop Control */
void CLOCK_Module_Stop_Cmd(clock_module_stop_te module, FunctionState state);

/* Clock Measure Function */
float CLOCK_Measurement(clock_measurement_source_te source);
/*!<---------------End of APIs--------------->!*/
#endif
/*!<---------------End of _LT168_CLOCK_H --------------->!*/
///*
// * @Author: Laputa
// * @Version: V0.0
// * @Date: 2023-09-15 16:44:57
// * @LastEditors: Laputa
// * @LastEditTime: 2023-09-23 16:59:45
// * @Description: This file contains the functions prototypes for the CLOCK firmware library.
// *
// * Copyright (c) 2023 by Levetop, All Rights Reserved.
// */
//
//#ifndef _LT168_CLOCK_H
//#define _LT168_CLOCK_H
//
//#include "LT168.h"
//
//
//extern uint32_t SYS_CLOCK;
//extern uint32_t OSC;//婢舵牠鍎撮弮鍫曟寭
//
///*
//1. 1MHz <= XIN/N <= 50MHZ
//2. 200MHz <= XIN*M/N <= 400MHz
//3. M
//4. N
//*/
//typedef struct
//{
//	unsigned short M;	//4<=M , 4-16383
//	unsigned char  N;	//1<=N , 1-15
//	unsigned char OD;	//0-3, 2^OD (1,2,4,8)
//	unsigned char DIV;	//0-63, 0: by 2,DRV = value*2;
//	unsigned long OSC;	//婢舵牠鍎撮弲鑸靛盁閸ュ搫鐣炬稉锟�2MHz
//}PLL_Set_parameter;
//
//uint32_t Get_SysClock(void);
//void Clock_Init(UINT32 sys_clk_mhz);
//
///*******************************************************************************
// * Definitions
// ******************************************************************************/
//
///* SYNCR */
//#define CLOCK_SYNCR_LOSCLPEN_MASK                        (0x1U)
//#define CLOCK_SYNCR_LOSCLPEN_SHIFT                       (0U)
//#define CLOCK_SYNCR_LOSCLPEN(x)                          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_LOSCLPEN_SHIFT)) & CLOCK_SYNCR_LOSCLPEN_MASK)
//
//#define CLOCK_SYNCR_ADCEN_MASK                           (0x4U)
//#define CLOCK_SYNCR_ADCEN_SHIFT                          (2U)
//#define CLOCK_SYNCR_ADCEN(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ADCEN_SHIFT)) & CLOCK_SYNCR_ADCEN_MASK)
//
//#define CLOCK_SYNCR_CACHERAMLPEN_MASK                    (0x8U)
//#define CLOCK_SYNCR_CACHERAMLPEN_SHIFT                   (3U)
//#define CLOCK_SYNCR_CACHERAMLPEN(x)                      (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_CACHERAMLPEN_SHIFT)) & CLOCK_SYNCR_CACHERAMLPEN_MASK)
//
//#define CLOCK_SYNCR_STBYMD_MASK                          (0x30U)
//#define CLOCK_SYNCR_STBYMD_SHIFT                         (4U)
//#define CLOCK_SYNCR_STBYMD(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_STBYMD_SHIFT)) & CLOCK_SYNCR_STBYMD_MASK)
//
//#define CLOCK_SYNCR_CLKOUTSEL_MASK                       (0x40U)
//#define CLOCK_SYNCR_CLKOUTSEL_SHIFT                      (6U)
//#define CLOCK_SYNCR_CLKOUTSEL(x)                         (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_CLKOUTSEL_SHIFT)) & CLOCK_SYNCR_CLKOUTSEL_MASK)
//
//#define CLOCK_SYNCR_DISPLAYRAMLPEN_MASK                  (0x80U)
//#define CLOCK_SYNCR_DISPLAYRAMLPEN_SHIFT                 (7U)
//#define CLOCK_SYNCR_DISPLAYRAMLPEN(x)                    (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_DISPLAYRAMLPEN_SHIFT)) & CLOCK_SYNCR_DISPLAYRAMLPEN_MASK)
//
//#define CLOCK_SYNCR_SLEEP_MASK                           (0x100U)
//#define CLOCK_SYNCR_SLEEP_SHIFT                          (8U)
//#define CLOCK_SYNCR_SLEEP(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SLEEP_SHIFT)) & CLOCK_SYNCR_SLEEP_MASK)
//
//#define CLOCK_SYNCR_PLLEN_MASK                           (0x200U)
//#define CLOCK_SYNCR_PLLEN_SHIFT                          (9U)
//#define CLOCK_SYNCR_PLLEN(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLEN_SHIFT)) & CLOCK_SYNCR_PLLEN_MASK)
//
//#define CLOCK_SYNCR_PLLSRCEN_MASK                        (0x400U)
//#define CLOCK_SYNCR_PLLSRCEN_SHIFT                       (10U)
//#define CLOCK_SYNCR_PLLSRCEN(x)                          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLSRCEN_SHIFT)) & CLOCK_SYNCR_PLLSRCEN_MASK)
//
//#define CLOCK_SYNCR_LOSCEN_MASK                          (0x800U)
//#define CLOCK_SYNCR_LOSCEN_SHIFT                         (11U)
//#define CLOCK_SYNCR_LOSCEN(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_LOSCEN_SHIFT)) & CLOCK_SYNCR_LOSCEN_MASK)
//
//#define CLOCK_SYNCR_ADCDIV_MASK                          (0xF000U)
//#define CLOCK_SYNCR_ADCDIV_SHIFT                         (12U)
//#define CLOCK_SYNCR_ADCDIV(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ADCDIV_SHIFT)) & CLOCK_SYNCR_ADCDIV_MASK)
//
//#define CLOCK_SYNCR_PLLDIV_MASK                          (0xFC0000U)
//#define CLOCK_SYNCR_PLLDIV_SHIFT                         (18U)
//#define CLOCK_SYNCR_PLLDIV(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLDIV_SHIFT)) & CLOCK_SYNCR_PLLDIV_MASK)
//
//#define CLOCK_SYNCR_ENLOWPOWER_MASK                      (0x1000000U)
//#define CLOCK_SYNCR_ENLOWPOWER_SHIFT                     (24U)
//#define CLOCK_SYNCR_ENLOWPOWER(x)                        (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_ENLOWPOWER_SHIFT)) & CLOCK_SYNCR_ENLOWPOWER_MASK)
//
//#define CLOCK_SYNCR_PLLOCKM_MASK                         (0x2000000U)
//#define CLOCK_SYNCR_PLLOCKM_SHIFT                        (25U)
//#define CLOCK_SYNCR_PLLOCKM(x)                           (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_PLLOCKM_SHIFT)) & CLOCK_SYNCR_PLLOCKM_MASK)
//
//#define CLOCK_SYNCR_SYSRAM0LPEN_MASK                     (0x4000000U)
//#define CLOCK_SYNCR_SYSRAM0LPEN_SHIFT                    (26U)
//#define CLOCK_SYNCR_SYSRAM0LPEN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM0LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM0LPEN_MASK)
//
//#define CLOCK_SYNCR_SYSRAM1LPEN_MASK                     (0x8000000U)
//#define CLOCK_SYNCR_SYSRAM1LPEN_SHIFT                    (27U)
//#define CLOCK_SYNCR_SYSRAM1LPEN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM1LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM1LPEN_MASK)
//
//#define CLOCK_SYNCR_SYSRAM2LPEN_MASK                     (0x10000000U)
//#define CLOCK_SYNCR_SYSRAM2LPEN_SHIFT                    (28U)
//#define CLOCK_SYNCR_SYSRAM2LPEN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM2LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM2LPEN_MASK)
//
//#define CLOCK_SYNCR_SYSRAM3LPEN_MASK                     (0x20000000U)
//#define CLOCK_SYNCR_SYSRAM3LPEN_SHIFT                    (29U)
//#define CLOCK_SYNCR_SYSRAM3LPEN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYSRAM3LPEN_SHIFT)) & CLOCK_SYNCR_SYSRAM3LPEN_MASK)
//
//#define CLOCK_SYNCR_SYNCTEST_MASK                        (0xC0000000U)
//#define CLOCK_SYNCR_SYNCTEST_SHIFT                       (30U)
//#define CLOCK_SYNCR_SYNCTEST(x)                          (((uint32_t)(((uint32_t)(x)) << CLOCK_SYNCR_SYNCTEST_SHIFT)) & CLOCK_SYNCR_SYNCTEST_MASK)
//
///* LOSCCSR */
//#define CLOCK_LOSCCSR_SXOSCEN_MASK                       (0x1U)
//#define CLOCK_LOSCCSR_SXOSCEN_SHIFT                      (0U)
//#define CLOCK_LOSCCSR_SXOSCEN(x)                         (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SXOSCEN_SHIFT)) & CLOCK_LOSCCSR_SXOSCEN_MASK)
//
//#define CLOCK_LOSCCSR_WDTCLKSEL_MASK                     (0x2U)
//#define CLOCK_LOSCCSR_WDTCLKSEL_SHIFT                    (1U)
//#define CLOCK_LOSCCSR_WDTCLKSEL(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_WDTCLKSEL_SHIFT)) & CLOCK_LOSCCSR_WDTCLKSEL_MASK)
//
//#define CLOCK_LOSCCSR_WDTCLKCHGDONE_MASK                 (0x20U)
//#define CLOCK_LOSCCSR_WDTCLKCHGDONE_SHIFT                (5U)
//
//#define CLOCK_LOSCCSR_SXOSCRD_MASK                       (0x40U)
//#define CLOCK_LOSCCSR_SXOSCRD_SHIFT                      (6U)
//
//#define CLOCK_LOSCCSR_SIRCRDY_MASK                       (0x80U)
//#define CLOCK_LOSCCSR_SIRCRDY_SHIFT                      (7U)
//
//#define CLOCK_LOSCCSR_SXOSCST_MASK                       (0xFFFF00U)
//#define CLOCK_LOSCCSR_SXOSCST_SHIFT                      (8U)
//#define CLOCK_LOSCCSR_SXOSCST(x)                         (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SXOSCST_SHIFT)) & CLOCK_LOSCCSR_SXOSCST_MASK)
//
//#define CLOCK_LOSCCSR_SIRCST_MASK                        (0x1F000000U)
//#define CLOCK_LOSCCSR_SIRCST_SHIFT                       (24U)
//#define CLOCK_LOSCCSR_SIRCST(x)                          (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_SIRCST_SHIFT)) & CLOCK_LOSCCSR_SIRCST_MASK)
//
//#define CLOCK_LOSCCSR_LOSCCSTEST_MASK                    (0xC0000000U)
//#define CLOCK_LOSCCSR_LOSCCSTEST_SHIFT                   (30U)
//#define CLOCK_LOSCCSR_LOSCCSTEST(x)                      (((uint32_t)(((uint32_t)(x)) << CLOCK_LOSCCSR_LOSCCSTEST_SHIFT)) & CLOCK_LOSCCSR_LOSCCSTEST_MASK)
//
//
///* PLLCSR */
//#define CLOCK_PLLCSR_PLLM_MASK                           (0x3FFFU)
//#define CLOCK_PLLCSR_PLLM_SHIFT                          (0U)
//#define CLOCK_PLLCSR_PLLM(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLM_SHIFT)) & CLOCK_PLLCSR_PLLM_MASK)
//
//#define CLOCK_PLLCSR_PLLOD_MASK                          (0xC000U)
//#define CLOCK_PLLCSR_PLLOD_SHIFT                         (14U)
//#define CLOCK_PLLCSR_PLLOD(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLOD_SHIFT)) & CLOCK_PLLCSR_PLLOD_MASK)
//
//#define CLOCK_PLLCSR_PLLN_MASK                           (0xF0000U)
//#define CLOCK_PLLCSR_PLLN_SHIFT                          (16U)
//#define CLOCK_PLLCSR_PLLN(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLN_SHIFT)) & CLOCK_PLLCSR_PLLN_MASK)
//
//#define CLOCK_PLLCSR_PLLOCK_MASK                         (0x01000000U)
//#define CLOCK_PLLCSR_PLLOCK_SHIFT                        (24U)
//
//#define CLOCK_PLLCSR_PLLCSRTEST_MASK                     (0xC0000000U)
//#define CLOCK_PLLCSR_PLLCSRTEST_SHIFT                    (30U)
//#define CLOCK_PLLCSR_PLLCSRTEST(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_PLLCSR_PLLCSRTEST_SHIFT)) & CLOCK_PLLCSR_PLLCSRTEST_MASK)
//
///* MSCR */
//
//#define CLOCK_MSCR_BLENDER_MASK                          (0x1U)
//#define CLOCK_MSCR_BLENDER_SHIFT                         (0U)
//#define CLOCK_MSCR_BLENDER(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_BLENDER_SHIFT)) & CLOCK_MSCR_BLENDER_MASK)
//
//#define CLOCK_MSCR_COMP0_MASK                            (0x2U)
//#define CLOCK_MSCR_COMP0_SHIFT                           (1U)
//#define CLOCK_MSCR_COMP0(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_COMP0_SHIFT)) & CLOCK_MSCR_COMP0_MASK)
//
//#define CLOCK_MSCR_COMP1_MASK                            (0x4U)
//#define CLOCK_MSCR_COMP1_SHIFT                           (2U)
//#define CLOCK_MSCR_COMP1(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_COMP1_SHIFT)) & CLOCK_MSCR_COMP1_MASK)
//
//#define CLOCK_MSCR_ADC_MASK                              (0x8U)
//#define CLOCK_MSCR_ADC_SHIFT                             (3U)
//#define CLOCK_MSCR_ADC(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_ADC_SHIFT)) & CLOCK_MSCR_ADC_MASK)
//
//#define CLOCK_MSCR_PIT0_MASK                             (0x10U)
//#define CLOCK_MSCR_PIT0_SHIFT                            (4U)
//#define CLOCK_MSCR_PIT0(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT0_SHIFT)) & CLOCK_MSCR_PIT0_MASK)
//
//#define CLOCK_MSCR_PIT1_MASK                             (0x20U)
//#define CLOCK_MSCR_PIT1_SHIFT                            (5U)
//#define CLOCK_MSCR_PIT1(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT1_SHIFT)) & CLOCK_MSCR_PIT1_MASK)
//
//#define CLOCK_MSCR_PIT2_MASK                             (0x40U)
//#define CLOCK_MSCR_PIT2_SHIFT                            (6U)
//#define CLOCK_MSCR_PIT2(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT2_SHIFT)) & CLOCK_MSCR_PIT2_MASK)
//
//#define CLOCK_MSCR_PIT3_MASK                             (0x80U)
//#define CLOCK_MSCR_PIT3_SHIFT                            (7U)
//#define CLOCK_MSCR_PIT3(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PIT3_SHIFT)) & CLOCK_MSCR_PIT3_MASK)
//
//#define CLOCK_MSCR_RTC_MASK                              (0x100U)
//#define CLOCK_MSCR_RTC_SHIFT                             (8U)
//#define CLOCK_MSCR_RTC(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RTC_SHIFT)) & CLOCK_MSCR_RTC_MASK)
//
//#define CLOCK_MSCR_DMA_MASK                              (0x200U)
//#define CLOCK_MSCR_DMA_SHIFT                             (9U)
//#define CLOCK_MSCR_DMA(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_DMA_SHIFT)) & CLOCK_MSCR_DMA_MASK)
//
//#define CLOCK_MSCR_PWM0_MASK                             (0x400U)
//#define CLOCK_MSCR_PWM0_SHIFT                            (10U)
//#define CLOCK_MSCR_PWM0(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PWM0_SHIFT)) & CLOCK_MSCR_PWM0_MASK)
//
//#define CLOCK_MSCR_PWM1_MASK                             (0x800U)
//#define CLOCK_MSCR_PWM1_SHIFT                            (11U)
//#define CLOCK_MSCR_PWM1(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_PWM1_SHIFT)) & CLOCK_MSCR_PWM1_MASK)
//
//#define CLOCK_MSCR_EPORT0_MASK                           (0x1000U)
//#define CLOCK_MSCR_EPORT0_SHIFT                          (12U)
//#define CLOCK_MSCR_EPORT0(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT0_SHIFT)) & CLOCK_MSCR_EPORT0_MASK)
//
//#define CLOCK_MSCR_EPORT1_MASK                           (0x2000U)
//#define CLOCK_MSCR_EPORT1_SHIFT                          (13U)
//#define CLOCK_MSCR_EPORT1(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT1_SHIFT)) & CLOCK_MSCR_EPORT1_MASK)
//
//#define CLOCK_MSCR_XBAR_MASK                             (0x4000U)
//#define CLOCK_MSCR_XBAR_SHIFT                            (14U)
//#define CLOCK_MSCR_XBAR(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_XBAR_SHIFT)) & CLOCK_MSCR_XBAR_MASK)
//
//#define CLOCK_MSCR_OPTION_MASK                           (0x8000U)
//#define CLOCK_MSCR_OPTION_SHIFT                          (15U)
//#define CLOCK_MSCR_OPTION(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_OPTION_SHIFT)) & CLOCK_MSCR_OPTION_MASK)
//
//#define CLOCK_MSCR_RESET_MASK                            (0x10000U)
//#define CLOCK_MSCR_RESET_SHIFT                           (16U)
//#define CLOCK_MSCR_RESET(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RESET_SHIFT)) & CLOCK_MSCR_RESET_MASK)
//
//#define CLOCK_MSCR_WDT_MASK                              (0x20000U)
//#define CLOCK_MSCR_WDT_SHIFT                             (17U)
//#define CLOCK_MSCR_WDT(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_WDT_SHIFT)) & CLOCK_MSCR_WDT_MASK)
//
//#define CLOCK_MSCR_SCI0_MASK                             (0x40000U)
//#define CLOCK_MSCR_SCI0_SHIFT                            (18U)
//#define CLOCK_MSCR_SCI0(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI0_SHIFT)) & CLOCK_MSCR_SCI0_MASK)
//
//#define CLOCK_MSCR_CCM_MASK                              (0x80000U)
//#define CLOCK_MSCR_CCM_SHIFT                             (19U)
//#define CLOCK_MSCR_CCM(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_CCM_SHIFT)) & CLOCK_MSCR_CCM_MASK)
//
//#define CLOCK_MSCR_I2C_MASK                              (0x100000U)
//#define CLOCK_MSCR_I2C_SHIFT                             (20U)
//#define CLOCK_MSCR_I2C(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_I2C_SHIFT)) & CLOCK_MSCR_I2C_MASK)
//
//#define CLOCK_MSCR_SCI1_MASK                             (0x200000U)
//#define CLOCK_MSCR_SCI1_SHIFT                            (21U)
//#define CLOCK_MSCR_SCI1(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI1_SHIFT)) & CLOCK_MSCR_SCI1_MASK)
//
//#define CLOCK_MSCR_SCI2_MASK                             (0x400000U)
//#define CLOCK_MSCR_SCI2_SHIFT                            (22U)
//#define CLOCK_MSCR_SCI2(x)                               (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SCI2_SHIFT)) & CLOCK_MSCR_SCI2_MASK)
//
//#define CLOCK_MSCR_CAN_MASK                              (0x800000U)
//#define CLOCK_MSCR_CAN_SHIFT                             (23U)
//#define CLOCK_MSCR_CAN(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_CAN_SHIFT)) & CLOCK_MSCR_CAN_MASK)
//
//#define CLOCK_MSCR_EPORT2_MASK                           (0x1000000U)
//#define CLOCK_MSCR_EPORT2_SHIFT                          (24U)
//#define CLOCK_MSCR_EPORT2(x)                             (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_EPORT2_SHIFT)) & CLOCK_MSCR_EPORT2_MASK)
//
//#define CLOCK_MSCR_QSPI0_MASK                            (0x2000000U)
//#define CLOCK_MSCR_QSPI0_SHIFT                           (25U)
//#define CLOCK_MSCR_QSPI0(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI0_SHIFT)) & CLOCK_MSCR_QSPI0_MASK)
//
//#define CLOCK_MSCR_QSPI1_MASK                            (0x4000000U)
//#define CLOCK_MSCR_QSPI1_SHIFT                           (26U)
//#define CLOCK_MSCR_QSPI1(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI1_SHIFT)) & CLOCK_MSCR_QSPI1_MASK)
//
//#define CLOCK_MSCR_QSPI2_MASK                            (0x8000000U)
//#define CLOCK_MSCR_QSPI2_SHIFT                           (27U)
//#define CLOCK_MSCR_QSPI2(x)                              (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_QSPI2_SHIFT)) & CLOCK_MSCR_QSPI2_MASK)
//
//#define CLOCK_MSCR_RGB_MASK                              (0x10000000U)
//#define CLOCK_MSCR_RGB_SHIFT                             (28U)
//#define CLOCK_MSCR_RGB(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_RGB_SHIFT)) & CLOCK_MSCR_RGB_MASK)
//
//#define CLOCK_MSCR_USB_MASK                              (0x20000000U)
//#define CLOCK_MSCR_USB_SHIFT                             (29U)
//#define CLOCK_MSCR_USB(x)                                (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_USB_SHIFT)) & CLOCK_MSCR_USB_MASK)
//
//
//
//#define CLOCK_MSCR_SYNCTEST_MASK                        (0xC0000000U)
//#define CLOCK_MSCR_SYNCTEST_SHIFT                       (30U)
//#define CLOCK_MSCR_SYNCTEST(x)                          (((uint32_t)(((uint32_t)(x)) << CLOCK_MSCR_SYNCTEST_SHIFT)) & CLOCK_MSCR_SYNCTEST_MASK)
//
///* ECSECR */
//
//#define CLOCK_ECSECR_EPTEN_MASK                          (0x800000U)
//#define CLOCK_ECSECR_EPTEN_SHIFT                         (23U)
//#define CLOCK_ECSECR_EPTEN(x)                            (((uint32_t)(((uint32_t)(x)) << CLOCK_ECSECR_EPTEN_SHIFT)) & CLOCK_ECSECR_EPTEN_MASK)
//
//#define CLOCK_ECSECR_EPTDIV_MASK                         (0xFF000000U)
//#define CLOCK_ECSECR_EPTDIV_SHIFT                        (24U)
//#define CLOCK_ECSECR_EPTDIV(x)                           (((uint32_t)(((uint32_t)(x)) << CLOCK_ECSECR_EPTDIV_SHIFT)) & CLOCK_ECSECR_EPTDIV_MASK)
//
///* OBTCR1 */
//#define CLOCK_OBTCR1_BIST_TARGET_MASK                    (0xFFFFU)
//#define CLOCK_OBTCR1_BIST_TARGET_SHIFT                   (0U)
//#define CLOCK_OBTCR1_BIST_TARGET(x)                      (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR1_BIST_TARGET_SHIFT)) & CLOCK_OBTCR1_BIST_TARGET_MASK)
//
//#define CLOCK_OBTCR1_BIST_HOLD_TARGET_MASK               (0xFFFF0000U)
//#define CLOCK_OBTCR1_BIST_HOLD_TARGET_SHIFT              (16U)
//#define CLOCK_OBTCR1_BIST_HOLD_TARGET(x)                 (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR1_BIST_HOLD_TARGET_SHIFT)) & CLOCK_OBTCR1_BIST_HOLD_TARGET_MASK)
//
///* OBTCR2 */
//#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_MASK         (0xFFFFU)
//#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_SHIFT        (0U)
//#define CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN(x)           (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_SHIFT)) & CLOCK_OBTCR2_BIST_TEST_CTRIM_MARGIN_MASK)
//
//#define CLOCK_OBTCR2_BIST_TEST_TARGET_MASK               (0xFFFF0000U)
//#define CLOCK_OBTCR2_BIST_TEST_TARGET_SHIFT              (16U)
//#define CLOCK_OBTCR2_BIST_TEST_TARGET(x)                 (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR2_BIST_TEST_TARGET_SHIFT)) & CLOCK_OBTCR2_BIST_TEST_TARGET_MASK)
//
///* OBTCR */
//#define CLOCK_OBTCR_BIST_EN_MASK                         (0x100U)
//#define CLOCK_OBTCR_BIST_EN_SHIFT                        (8U)
//#define CLOCK_OBTCR_BIST_EN(x)                           (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_EN_SHIFT)) & CLOCK_OBTCR_BIST_EN_MASK)
//
//#define CLOCK_OBTCR_BIST_IRC_SEL_MASK                    (0x200U)
//#define CLOCK_OBTCR_BIST_IRC_SEL_SHIFT                   (9U)
//#define CLOCK_OBTCR_BIST_IRC_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_IRC_SEL_SHIFT)) & CLOCK_OBTCR_BIST_IRC_SEL_MASK)
//
//#define CLOCK_OBTCR_BIST_IRC_EN_MASK                     (0x400U)
//#define CLOCK_OBTCR_BIST_IRC_EN_SHIFT                    (10U)
//#define CLOCK_OBTCR_BIST_IRC_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_IRC_EN_SHIFT)) & CLOCK_OBTCR_BIST_IRC_EN_MASK)
//
//#define CLOCK_OBTCR_BIST_VAL_INV_MASK                    (0x800U)
//#define CLOCK_OBTCR_BIST_VAL_INV_SHIFT                   (11U)
//#define CLOCK_OBTCR_BIST_VAL_INV(x)                      (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_VAL_INV_SHIFT)) & CLOCK_OBTCR_BIST_VAL_INV_MASK)
//
//#define CLOCK_OBTCR_BIST_MODE_MASK                       (0x1000U)
//#define CLOCK_OBTCR_BIST_MODE_SHIFT                      (12U)
//#define CLOCK_OBTCR_BIST_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_MODE_SHIFT)) & CLOCK_OBTCR_BIST_MODE_MASK)
//
//#define CLOCK_OBTCR_BIST_RESETN_MASK                     (0x2000U)
//#define CLOCK_OBTCR_BIST_RESETN_SHIFT                    (13U)
//#define CLOCK_OBTCR_BIST_RESETN(x)                       (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_RESETN_SHIFT)) & CLOCK_OBTCR_BIST_RESETN_MASK)
//
//#define CLOCK_OBTCR_BIST_START_MASK                      (0x8000U)
//#define CLOCK_OBTCR_BIST_START_SHIFT                     (15U)
//#define CLOCK_OBTCR_BIST_START(x)                        (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_START_SHIFT)) & CLOCK_OBTCR_BIST_START_MASK)
//
//#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_MASK          (0xFFFF0000U)
//#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_SHIFT         (16U)
//#define CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN(x)            (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_SHIFT)) & CLOCK_OBTCR_BIST_TEST_FTRIM_MARGIN_MASK)
//
///* OBTCNTR */
//#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE_MASK              (0x1FU)
//#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE_SHIFT             (0U)
//#define CLOCK_OBTCNTR_BIST_FTRIM_TRACE(x)                (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_FTRIM_TRACE_SHIFT)) & CLOCK_OBTCNTR_BIST_FTRIM_TRACE_MASK)
//
//#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE_MASK              (0x1F00U)
//#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE_SHIFT             (8U)
//#define CLOCK_OBTCNTR_BIST_CTRIM_TRACE(x)                (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_CTRIM_TRACE_SHIFT)) & CLOCK_OBTCNTR_BIST_CTRIM_TRACE_MASK)
//
//#define CLOCK_OBTCNTR_BIST_TEST_CNT_MASK                 (0xFFFF0000U)
//#define CLOCK_OBTCNTR_BIST_TEST_CNT_SHIFT                (16U)
//#define CLOCK_OBTCNTR_BIST_TEST_CNT(x)                   (((uint32_t)(((uint32_t)(x)) << CLOCK_OBTCNTR_BIST_TEST_CNT_SHIFT)) & CLOCK_OBTCNTR_BIST_TEST_CNT_MASK)
//
///* OBTRR */
//#define CLOCK_OBTRR_BISTRESULT_MASK                      (0x1FFFFU)
//#define CLOCK_OBTRR_BISTRESULT_SHIFT                     (0U)
//
//#define CLOCK_OBTRR_BIST_PASS_MASK                       (0x1000000U)
//#define CLOCK_OBTRR_BIST_PASS_SHIFT                      (24U)
//
//#define CLOCK_OBTRR_BIST_DONE_MASK                       (0x2000000U)
//#define CLOCK_OBTRR_BIST_DONE_SHIFT                      (25U)
//
//
//
///*!<---------------End of Definitions--------------->!*/
//
//
//
///*******************************************************************************
// * APIs
// ******************************************************************************/
//
//
///*!<---------------End of APIs--------------->!*/
//#endif
///*!<---------------End of _LT168_CLOCK_H --------------->!*/
